1. Field of the Invention
The present invention generally relates to the design of semiconductor chips and integrated circuits, and more particularly to a method of inserting spare cell locations in an integrated circuit design to accommodate engineering changes.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells.
An IC chip is fabricated by first conceiving a logical (behavioral) description for the circuit, and converting that logical description into a physical description, or geometric layout. This process is carried out in steps, such as first generating a register-transfer level (RTL) description of the circuit based on the logical description, and then using logic synthesis to derive a gate level description or “netlist.” A netlist is a record of all of the nets (interconnections) between cell pins, including information about the various components such as transistors, resistors and capacitors. The circuit layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements, and may go through several iterations of analysis and refinement.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located in a layer of an integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices such as microprocessors and application-specific integrated circuits (ASICs), physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different hardware-description programming languages (HDL) have been created for electronic design automation, including Verilog, C, VHDL and TDML. A typical electronic design automation system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Once a design is mostly finished, slight modifications may still be required to meet last-minute changes to specifications or for other reasons, usually relayed as an engineering change order (ECO). Because the circuit design is substantially complete (i.e., it conforms to various design requirements such as timing and slew), it is important to minimize the impact of any changes which might otherwise lead to violations and thus require additional iterations of the design steps, meaning significant computational expense. In order to alleviate this predicament, designers place filler (ECO) cells in the circuit design which have no function other than providing spare locations as needed for later changes. These spare locations can be provided in additional to surplus latches that are inserted in a design. A certain percentage of the total number of cells is designated for filler cells, and those cells are randomly placed throughout the layout.
In a traditional synthesis environment, as illustrated by FIG. 1, spare gate insertion has been a post placement, rule-based procedure. The design process begins with placement directed synthesis (2), followed by early mode padding (4). Placement directed synthesis is generally the step-by-step integration of logic synthesis and placement to overcome problems in achieving timing closure, and may for example include technology mapping, physical placement, electrical correction, and timing legalization. Early mode padding refers to insertion of delay cells (pads) along faster paths in the circuit design in order to correct early-mode timing violations. After these steps are completely finished, spare cells are inserted into the design (6). The process then continues to design routing (wiring) to properly connect the placed components while obeying all design rules for the integrated circuit (8).
The use of spare cells greatly simplifies implementation of ECOs but there can still be problems with the locations of these cells. Since the filler percentage is applied globally to an entire design, some areas of the circuit which are more stable can end up getting too many filler cells, while other areas do not get enough. Furthermore, typical placement tools can push filler cells away from the most critical logic (which is often unstable), so even though there are filler cells available, they are not located close enough to be of use for timing/logic fixes. Placement tools that partition the logic into separate bins can experience additional stability issues whenever the bin sizes or locations change.
Placement tools (particularly those which attempt to minimize wire length using quadratic placement) naturally pull connected logic together very tightly. This logic clustering effect can be countered by introducing a spreading factor to artificially increase instance sizes globally in a circuit design or portion thereof, i.e., a macro. Forcing cells within the macro to separate in this manner also improves routing and congestion issues. However, this spreading force is not effective for ECO work because it adds only a small amount of space to a large region instead of targeting areas that have a higher potential to change. These problems are exacerbated in high density circuit designs which have gone through multiple ECOs. The interior filler cells are exhausted early on, leaving an insufficient number of spare cell locations that are still close enough to associated logic gates.
In light of the foregoing, it would be desirable to devise an improved method of placing spare cell locations in an integrated circuit design which could avoid clustering problems associated with conventional placement tools. It would be further advantageous if the method could increase availability of spare cells for portions of an integrated circuit design which may be less stable.